1 ps8465c 09/07/05 1 2 3 v ss0 4 v dd1 5 sdram1 6 sdram3 7 v ss1 8 sdram2 9 v dd2 10 11 12 13 14 v dd5 sdram6 v ss5 sdram5 sdram4 v ss4 oe v dd3 sdram9 v ss3 v ssiic sclock 27 28 26 25 24 23 22 21 20 19 18 17 16 15 v dd0 sdram0 buf_in sdram8 v ss2 sdata v ddiic v dd4 sdram7 diagram description the pi6c182b is a high-speed low-noise 1-10 non-inverting buffer designed for sdram clock buffer applications and supports higher frequencies up to 140 mhz. at power up all sdram output are enabled and active. the i 2 c serial control may be used to individually activate/deactivate any of the 10 output drivers. the output enable (oe) pin may be pulled low to hi-z state on all outputs. note: purchase of i 2 c components from pericom conveys a license to use them in an i 2 c system as defned by philips. features ? low noise non-inverting 1-10 buffer ? supports frequency up to 140 mhz ? supports up to four sdram dimms ? low skew (<200ps) between any two output clocks ? i 2 c serial confguration interface ? multiple v dd , v ss pins for noise reduction ? 3.3v power supply voltage ? separate hi-z state pin for testing ? industrial temperature range (-40c to +85c) ? packaging: (pb-free & green available) 28-pin ssop (h) pin confguration precision 1-10 clock buffer pi6c182b sdram17 sdram2 sdram1 sdram0 buf_in oe sdata sclock sdram3 i 2 c i/o
pi6c182b precision 1-10 clock buffer 2 ps8465c 09/07/05 pin description pin symbol type qty description 2, 3, 6, 7 sdram[0-3] o 4 sdram byte 0 clock output 22, 23, 26, 27 sdram[4-7] o 4 sdram byte 1 clock output 11, 18 sdram[8-9] o 2 sdram byte 2 clock output 9 buf_in i 1 input for 1-20 buffer 20 oe i 1 hi-z states all outputs when held low. has a >100k? internal pull-up resistor. 14 sdata i/o 1 data pin for i 2 c curcuitry. has a >100k? internal pull-up resistor. 15 sclock i/o 1 clock pin i 2 c circuitry. has a >100k? internal pull-up resistor. 1, 5, 10, 19, 24, 28 vdd[0-5] power 6 3.3v power supply for sdram buffer 4, 8, 12, 17, 21, 25 vss[0-5] ground 6 ground for sdram buffers 13 vddiic power 1 3.3v power supply for i 2 c circuitry 16 vssiic ground 1 ground for i 2 c circuitry oe functionality oe sdram[0-9] notes 0 hi-z 1 1 buf_in 2 i 2 c address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 0 notes: 1. used for test purposes only 2. buffers are non-inverting serial confguration map byte0: sdram active/inactive register (1 = enable, 0 = disable) bit pin description 7 nc (initialize to 0) 6 nc (initialize to 0) 5 nc (initialize to 0) 4 nc (initialize to 0) 3 7 sdram3 (active/inactive) 2 6 sdram2 (active/inactive) 1 3 sdram1 (active/inactive) 0 2 sdram0 (active/inactive) note: 1. inactive means outputs are held low and are disabled from switching
pi6c182b precision 1-10 clock buffer 3 ps8465c 09/07/05 byte1: sdram active/inactive register (1 = enable, 0 = disable) bit pin description 7 27 sdram7 (active/inactive) 6 26 sdram6 (active/inactive) 5 23 sdram5 (active/inactive) 4 22 sdram4 (active/inactive) 3 nc (initialize to 0) 2 nc (initialize to 0) 1 nc (initialize to 0) 0 nc (initialize to 0) byte2: optional register for possible future requirements (1 = enable, 0 = disable) bit pin description 7 18 sdram9 (active/inactive) 6 11 sdram8 (active/inactive) 5 (reserved) 4 (reserved) 3 (reserved) 2 (reserved) 1 (reserved) 0 (reserved) 2-wire i2c control the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c182b is a slave receiver device. it can not be read back. sub addressing is not supported. all preceding bytes must be sent in order to change one of the control bytes. every byte put on the sdata line must be 8-bits long (msb frst), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclock is low. exceptions: a high to low transition on sdata while sclock is high indicates a start condition. a low to high transition on sdata while sclock is high is a stop condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the frst byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low = write to addressed device). if the devices own address is detected, pi6c182b generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. following acknowledgement of the address byte (d2), two more bytes must be sent: 1. command code byte 2. byte count byte. although the data bits on these two bytes are dont care, they must be sent and acknowledged. storage temperature ............................................................ C65c to +150c ambient temperature with power applied ........................... C40c to +85c 3.3v supply voltage to ground potential .............................. C0.5v to +4.6v dc input voltage ............................................................... ..... C0.5v to +4.6v note: stresses greater than those listed under maximum rat - ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for ex - tended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) supply current (v dd = +3.465v, c load = max.) symbol parameter test condidtion min. typ. max. units i dd supply current buf_in = 0 mhz 2 ma i dd buf_in = 66.66 mhz 180 i dd buf_in = 100.00 mhz 240 i dd buf_in = 133.00 mhz 360
pi6c182b precision 1-10 clock buffer 4 ps8465c 09/07/05 sdram clock buffer operating specifcation symbol parameter test conditions min. typ. max. units i ohmin pull-up current v out = 2.0v -54 ma i ohmax pull-up current v out = 3.135v -46 i olmin pull-down current v out = 1.0v 54 i olmax pull-down current v out = 0.4v 53 ac timing symbol parameter 66 mhz 100 mhz 133mhz units min. max. min. max. min. max. t sdrise sdram clk rise time 1.5 4.0 1.5 4.0 1.5 4.0 v/ns t sdfall sdram clk fall time 1.5 4.0 1.5 4.0 1.5 4.0 t plh sdram buffer lh prop delay 1.0 5.0 1.0 5.0 1.0 5.0 ns t phl sdram buffer hl prop delay 1.0 5.0 1.0 5.0 1.0 5.0 t pzl , t pzh sdram buffer enable delay (1) 1.0 8.0 1.0 8.0 1.0 8.0 t plz , t phz sdram buffer disable delay (1) 1.0 8.0 1.0 8.0 1.0 8.0 duty cycle measured at 1.5v 45 55 45 55 45 55 % t sdskw sdram output-to-output skew 250 250 200 ps dc operating specifcations (v dd = +3.3v 5%, t a = - 40c to + 85c) symbol parameter test conditions min. typ. max. units input voltage v ih input high voltage v dd 2.0 v dd +0.3 v v il input low voltage v ss -0.3 0.8 i il input leakage current 0 < v in < v dd -5 5 ma v dd [0-9] = 3.3v 5% v oh output high voltage i oh = -1ma 2.4 v v ol output low voltage i ol = 1ma 0.4 c out output pin capacitance 6 pf c in input pin capacitance 5 l pin pin inductance 7 nh t a ambient temperature no airfow 0 70 c note: 1. this parameter specifed at 5 mhz input frequency.
pi6c182b precision 1-10 clock buffer 5 ps8465c 09/07/05 figure 1. clock waveforms notes: 1. maximum rise/fall times are guaranteed at maximum specifed load. 2. minimum rise/fall times are guaranteed at minimum specifed load. 3. rise/fall times are specifed with pure capacitive load as shown. testing is done with an additional 500 resistor in parallel. minimum and maximum expected capacitive loads clock min. max. units notes sdram 15 20 pf sdram dimm specifcaion design guidelines to reduce emi 1. place series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10pf. series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specifed values. 2. minimize the number of vias of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. 1.5v 1.5v t phl t plh 1.5v 1.5v input waveform output waveform output buffer test point 2.4 1.5 0.4 tsdkh tsdkp 3.3v clocking interface (ttl) tsdkl t sdfall t sdrise test load
pi6c182b precision 1-10 clock buffer 6 ps8465c 09/07/05 pcb layout suggestion note: 1. this is only a suggested layout. there may be alternate solutions depending on actual pcb design and layout. 2. as a general rule, c1-c7 should be placed as close as possible to their respective vdd. 3. recommended capacitor values: c1-c7 = 0.1f, ceramic c8 = 22f c5 c6 c1 c7 c2 c3 c4 ferrite bead vcc c8 22uf via to gnd plane via to vdd plane void in power plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vdd vss vdd vss vss vdd vdd vdd vss vdd vss vss vdd vss figure 2. design guidelines sdram r s 10 cl pi6c182b sdram dimm spec. 100/66 mhz clock from chipset
pi6c182b precision 1-10 clock buffer 7 ps8465c 09/07/05 packaging mechanical: 28-pin ssop (h) pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ ordering information ordering code package code package type pi6c182bh h 28-pin ssop PI6C182BHE h pb-free & green, 28-pin ssop
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